High-level synthesis under multi-cycle interconnect delay
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ACM Press
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2015
2. Fast and effective placement and routing directed high-level synthesis for FPGAs;Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays;2014-02-26
3. Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2013
4. MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures;IEICE Electronics Express;2012
5. Timing variation-aware scheduling and resource binding in high-level synthesis;ACM Transactions on Design Automation of Electronic Systems;2011-10
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