Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA-Reference-Cited by-同舟云学术

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Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

Published:2010-08 Issue: Volume: Page:
ISSN:
Container-title:2010 International Conference on Field Programmable Logic and Applications
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Author:

Lhairech-Lebreton Ghizlane,Coussy Philippe,Martin Eric

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5690273/5694025/05694295.pdf?arnumber=5694295

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

3. Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis;Microprocessors and Microsystems;2023-10

4. PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis;Expert Systems with Applications;2023-08

5. The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image Processing;Journal of Signal Processing Systems;2023-07-29

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