1. [1] P. Beckett, “A low-power reconfigurable logic array based on double-gate transistors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.16, no.2, pp.115-123, Feb. 2008.
2. [3] I. O'Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, T. Dang, and R. Leveugle, “CNTFET modeling and reconfigurable Logic-circuit design,” IEEE Trans. Circuit Syst. I, vol.54, no.11, pp.2365-2379, Nov. 2007.
3. [4] T. Hayashi and S. Watanabe, “Circuit design of reconfigurable logic based on MOS double gate/carbon nanotube transistor,” IEICE Trans. Electron. (Japanese Edition), vol.J93-C, no.12, pp.674-675, Dec. 2010.
4. [5] K. Jabeur, N. Yakymets, I. O'Connor, and S. Le Beux, “Fine-grain reconfigurable logic cells based on double-gate CNTFETs,” Proc. ACM GLSVLSI'11, pp.19-24, 2011.
5. [6] K. Jabeur, N. Yakymets, I. O'Connor, and S. LeBeux, “Ambipolar double-gate FET binary-decision-diagram (Am-BDD) for reconfigurable logic cells,” Proc. 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH'11), pp.162-168, June 2011.