Reconfigurable Dynamic Logic Circuit Generating <i>t</i>-Term Boolean Functions Based on Double-Gate CNTFETs-Reference-Cited by-同舟云学术

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs

Published:2014 Issue:5 Volume:E97.A Page:1051-1058
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KOBAYASHI Manabu¹,NINOMIYA Hiroshi¹,MIURA Yasuyuki¹,WATANABE Shigeyoshi¹

Affiliation:

1. Department of Information Science, School of Engineering, Shonan Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/5/E97.A_1051/_pdf

Reference9 articles.

1. [1] I. Hassoune and I. O'Connor, “Double-gate MOSFET based reconfigurable cells,” Electron. Lett., vol.43, no.23, pp.1273-1274, 2007.

2. [2] I. O'Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, T.-T. Dang, and R. Leveugle, “CNTFET modeling and reconfigurable logic-circuit design,” IEEE Trans. Circuits Syst. I, Regular Papers, vol.54, no.11, pp.2365-2379, Nov. 2007.

3. [3] K. Jabeur, N. Yakymets, I. O'Connor, and S. Le Beux, “Fine-grain reconfigurable logic cells based on double-gate CNTFETs,” Proc. ACM GLSVLSI'11, pp.19-24, 2011.

4. [4] M. Kobayashi, H. Ninomiya, and S. Watanabe, “Circuit design of reconfigurable logic based on double-gate CNTFETs,” IEICE Trans. Fundamentals, vol.E96-A, no.7, pp.1642-1644, July 2013.

5. [5] T. Hayashi and Y. Watanabe, “Circuit design of reconfigurable logic based on MOS double gate/carbon nano tube transistor,” IEICE Trans. Electron. (Japanese Edition), vol.J93-C, no.12, pp.674-675, Dec. 2010.