Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs-Reference-Cited by-同舟云学术

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs

Published:2014 Issue:2 Volume:E97.A Page:675-678
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

NINOMIYA Hiroshi¹,KOBAYASHI Manabu¹,MIURA Yasuyuki¹,WATANABE Shigeyoshi¹

Affiliation:

1. Department of Information Science, Shonan Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/2/E97.A_675/_pdf

Reference11 articles.

1. [1] P. Beckett, “A low-power reconfigurable logic array based on double-gate transistors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.16, no.2, pp.115-123, Feb. 2008.

2. [2] I. Hassoune and I. O'Connor, “Double-gate MOSFET based on reconfigurable cells,” Electron. Lett., vol.43, no.23, pp.1273-1274, 8th Nov. 2007.

3. [3] I. O'Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, T. Dang, and R. Leveugle, “CNTFET modeling and reconfigurable logic-circuit design,” IEEE Trans. Circuits Syst. I, vol.54, no.11, pp.2365-2379, Nov. 2007.

4. [4] T. Hayashi and S. Watanabe, “Circuit design of reconfigurable logic based on MOS double gate/carbon nanotube transistor,” IEICE Trans. Electron. (Japanese Edition), vol.J93-C, no.12, pp.674-675, Dec. 2010.

5. [5] K. Jabeur, N. Yakymets, I. O'Connor, and S. Le Beux, “Fine-grain reconfigurable logic cells based on double-gate CNTFETs,” Proc. ACM GLSVLSI'11, pp.19-24, 2011.