Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation

Author:

PARK Yonghee1,CHOI Junghoe2,HONG Jisuk1,LEE Sanghoon1,YOO Moonhyun1,CHO Jundong3

Affiliation:

1. Semiconductor R&D Center, Samsung Electronics Co. Ltd.

2. Synopsys Korea

3. Sungkyunkwan University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference13 articles.

1. [1] K. Lucas, S. Baron, J. Belledent, R. Boone, A. Borjon, C. Couderc, K. Patterson, L. Riviere-Cazaux, Y. Rody, F. Sundermann, O. Toublan, Y. Trouiller, J.C. Urbani, and K. Wimmer, “Investigation of model-based physical design restriction, ” Proc. SPIE, vol.5756, 2005.

2. [2] J. Yang, L. Capodicci, and D.M. Sylvester, “Layout verification and optimization based on flexible design rules, ” Proc. SPIE, vol.6156, 2006.

3. [3] J. Ho, Y. Wang, J. Wu, and Y.-C. Hou, “Lithography-simulation-based design for manufacturability rule development: An integrated circuit design house's approach, ” J. Micro/Nanolith. MEMS MOEMS, vol.6, no.043008, 2007.

4. [4] S. Choi, D. Jung, J. Hong, J. Choi, M. Yoo, and J. Kong, “DFM based on layout restriction and process window verification for sub-60nm memory devices, ” Proc. SPIE, vol.6607, 2007.

5. [5] T. Jhaveri, V. Rovner, L. Pileggi, A.J. Strojwas, D. Motiani, V. Kheterpal, K.Y. Tong, T. Hersan, and D. Pandini, “Mazimization of layout printability/manufactura-bility by extreme layout regularity, ” J. Micro/Nanolith. MEMS MOEMS, vol.6, no.031011, 2007.

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