Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization-Reference-Cited by-同舟云学术

Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization

Published:2019-12-01 Issue:12 Volume:E102.A Page:1711-1719
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

HYUN Daijoon¹,JUNG Younggwang¹,SHIN Youngsoo¹

Affiliation:

1. School of Electrical Engineering, KAIST

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E102.A/12/E102.A_1711/_pdf

Reference18 articles.

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3. [3] A.J. Hazelton, A. Wüest, G. Hughes, L.C. Litt, and F. Goodwin, “Cost of ownership for future lithography technologies,” Proc. SPIE Advanced Lithography, pp.7140Q-1-7140Q-10, Dec. 2008. 10.1117/12.804711

4. [4] Y. Lin, B. Yu, B. Xu, and D.Z. Pan, “Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict,” Proc. Int. Conf. on Comput. Aided Des., pp.396-403, Nov. 2015. 10.1109/iccad.2015.7372597

5. [5] Greco et al., “Generation of des. shapes for confining stitch-induced via structures,” US Patent App. 8,806,393, Aug. 2014.