A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI
Author:
Affiliation:
1. Graduate school of Information, Production and Systems, Waseda University
2. Samsung R&D Institute Japan
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E104.A/2/E104.A_2020GCP0012/_pdf
Reference30 articles.
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2. [2] W.H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. Inst. of Radio Eng. (IRE), vol.24, no.9, pp.1163-1182, Sept. 1936. 10.1109/jrproc.1936.228468
3. [3] D.P. Nguyen, T. Pham, and A. Pham, “A 28-GHz symmetrical Doherty power amplifier using stacked-FET cells,” IEEE Trans. Microw. Theory Tech., vol.66, no.6, pp.2628-2637, June 2018. 10.1109/tmtt.2018.2816024
4. [4] N. Rostomyan, M. Özen, and P. Asbeck, “28GHz Doherty power amplifier in CMOS SOI with 28% back-off PAE,” IEEE Microw. Wireless Compon. Lett., vol.28, no.5, pp.446-448, May 2018. 10.1109/lmwc.2018.2813882
5. [5] N. Rostomyan, M. Özen, and P. Asbeck, “A Ka-band asymmetric dual input CMOS SOI Doherty power amplifier with 25dBm output power and high back-off efficiency,” Proc. IEEE Topical Conf. on RF/Microw. Power Amplifiers Wireless Radio Appl. (PAWR), pp.1-4, Jan. 2019. 10.1109/pawr.2019.8708739
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1. Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS;IEICE Transactions on Electronics;2023-07-01
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