Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS
Author:
Affiliation:
1. School of Fundamental Science and Engineering, Waseda University
2. Graduate School of Information, Production and Systems, Waseda University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E106.C/7/E106.C_2022CDP0002/_pdf
Reference32 articles.
1. [1] P.M. Asbeck, N. Rostomyan, M. Özen, B. Rabet, and J.A. Jayamon, “Power Amplifiers for mm-Wave 5G Applications: Technology Comparisons and CMOS-SOI Demonstration Circuits,” IEEE Trans. Microw. Theory Techn., vol.67, no.7, pp.3099-3109, July 2019. 10.1109/tmtt.2019.2896047
2. [2] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari, “A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS,” IEEE Journal of Solid State Circuits, vol.51, no.12, pp.3020-3036, Dec. 2016. 10.1109/jssc.2016.2606584
3. [3] S. Hu, F. Wang, and H. Wang, “2.1 A 28GHz/37GHz/39GHz Multiband Linear Doherty Power Amplifier for 5G Massive MIMO Applications,” IEEE ISSCC, pp.32-34, 2017. 10.1109/isscc.2017.7870246
4. [4] Y. Suzuki, K. Kawai, H. Okazaki, S. Narahashi, T. Asai, and Y. Okumura, “Experimental Investigations of 28-GHz-Band Power Amplifier for Massive MIMO Transmitter,” Proc. of APMC, pp.479-482, 2017. 10.1109/apmc.2017.8251485
5. [5] N. Rostomyan, M. Özen, and P. Asbeck, “A Ka-Band Asymmetric Dual Input CMOS SOI Doherty Power Amplifier With 25 dBm Output Power and High Back-OFF Efficiency,” Proc. IEEE PAWR, pp.1-4, 2019. 10.1109/pawr.2019.8708739
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