A Ka-Band Asymmetric Dual Input CMOS SOI Doherty Power Amplifier with 25 dBm Output Power and High Back-Off Efficiency

Author:

Rostomyan Narek,Ozen Mustafa,Asbeck Peter

Publisher

IEEE

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Circuits for 5G applications implemented in FD-SOI and RF/PD-SOI technologies;New Materials and Devices Enabling 5G Applications and Beyond;2024

2. A New Doherty Combiner with Wide Bandwidth for Magnitude and Phase Balance Compensation;Journal of Electromagnetic Engineering and Science;2023-07-31

3. Load Mismatch Compensation of Doherty Power Amplifier Using Dual-Input and Mode Reconfiguration Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

4. Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS;IEICE Transactions on Electronics;2023-07-01

5. A 29-dBm, 34% PAE E-Band Dual-Input Doherty Power Amplifier Using 40-nm GaN Technology;2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS);2022-10-16

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