An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors-Reference-Cited by-同舟云学术

An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors

Published:2017 Issue:12 Volume:E100.A Page:2901-2910
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LIAO Chien-Hui¹,WEN Charles H.-P.²

Affiliation:

1. Inst. of Communications Engineering, Dept. of Electrical and Computer Engineering, National Chiao Tung University

2. Dept. of Electrical and Computer Engineering, National Chiao Tung University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/12/E100.A_2901/_pdf

Reference23 articles.

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3. [3] W.L. Hung, G. Link, Y. Xie, N. Vijaykrishnan, and M. Irwin, “Interconnect and thermal-aware floorplanning for 3D microprocessors,” International Symposium on Quality Electronic Design (ISQED), pp.98-104, March 2006. 10.1109/isqed.2006.77

4. [4] Y. Hu, S. Chen, L. Peng, E. Song, and J.W. Choi, “Effective thermal control techniques for liquid-cooled 3D multi-core processors,” International Symposium on Quality Electronic Design (ISQED), pp.8-15, March 2013. 10.1109/isqed.2013.6523583

5. [5] Y. Chen, E. Kursun, D. Motschman, C. Johnson, and Y. Xie, “Through silicon via aware design planning for thermally efficient 3-D integrated circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.32, no.9, pp.1335-1346, Sept. 2013. 10.1109/tcad.2013.2261120