On the Voltage Dependent Series Resistance, Interface Traps, and Conduction Mechanisms in the Al/(Ti-doped DLC)/p-Si/Au Schottky Barrier Diodes (SBDs)

Abstract

In this study, Al-(Ti:DLC)-pSi/Au Schottky barrier diode (SBD) was manufactured instead of conventional metal / semiconductor (MS) with and without an interlayer and then several fundamental electrical-characteristics such as ideality factor (n), barrier height B series and shunt resistances (Rs, Rsh), concentration of acceptor atoms (NA), and width of depletion-layer (Wd) were derived from the forward-reverse bias current/voltage (I-V), capacitance and conductance as a function of voltage (C/G-V) data using various calculation-methods. Semi logarithmic IF-VF plot shows a linear behavior at lower-voltages and then departed from linearity as a result of the influence of series resistance/Rs and organic-interlayer. Three linear regions can be seen on the double-logarithmic IF-VF plot. with different slopes (1.28, 3.14, and 1.79) in regions with low, middle, and high forward bias, which are indicated that Ohmic-mechanism, trap-charge-limited-current (TCLC) mechanism, and space-charge-limited-current (SCLC) mechanism, respectively. Energy dependent surface states (Nss) vs (Ess-Ev) profile was also obtained from the Card-Rhoderick method by considering voltage-dependence of n and B and they were grown from the mid-gap energy up to the semiconductor's valance band (Ev). To see the impact of Rs for 1 MHz, the measured C/G-V graphs were amendment. All results are indicated that almost all electrical parameters and conduction mechanism are quite depending on Rs, Nss, and calculation method due the voltage dependent of them.