Design and Verification of Generic FIFO using Layered Test bench and Assertion Technique

Abstract

Verification is must to ensure that the design is an exact representation of the specifications of the design without any bugs. Verification helps to avoid surprisess at later time so that product can enter the market on time with good quality and less cost. In the present research work, synchronous generic FIFO is designed using Verilog. Here the pointers will indicate the status of the FIFO, the flag information’s like Full, Empty, Last, Second Last First and the FIFO will have a synchronous Reset ability and this FIFO is used as a DUT under verification environment. The verification is carried out using SystemVerilog layered testbench approach. As the designing of modules get complex, it is becoming more difficult to check that design, as it takes longer time to check all the combinations of design inputs. This problem can be solved by randomization and adding cover group and assertions. The verification plan involves test bench, verification properties, assertions, coverage sequences, application of test cases and verification procedures for the FIFO design. The functionality of the DUT is verified through layered testbench approach and coverage analysis. The response of DUT under random constrained inputs is compared with the predicted response in the scoreboard unit of the layered testbench. The research work achieved 80% code coverage and around 90% of functional coverage.