1.2 kV SiC MOSFETs with tapered buffer oxide for the suppression of the electric field crowding effect

Abstract

Abstract 1.2 kV silicon carbide (SiC) MOSFETs with buffered oxide, which have been developed to reduce the gate–drain charge (Q GD), have the problem that the electric field is crowded at the corners of the buffered oxide. In this paper, 1.2 kV SiC MOSFETs with tapered buffer oxide are proposed to suppress the electric field crowding effect. The devices with tapered buffer oxide having an angle of 40° demonstrate a maximum electric field at the gate oxide in the off-state (E ox,max) of 1.87 MV·cm−1, achieving a 13.4% reduction compared to devices with a conventional structure. Additionally, it is verified that the output characteristics of 1.2 kV SiC MOSFETs can be improved by applying tapered buffer oxide. This is because the junction FET region can be designed with high concentration through the suppression of the electric field of the tapered buffer oxide.