Oxide-semiconductor channel ferroelectric field-effect transistors for high-density memory applications: 3D NAND operation and the potential impact of in-plane polarization

Abstract

Abstract We have explored the 3D NAND memory operation of oxide-semiconductor (OS) channel ferroelectric FETs (FeFETs) by TCAD simulation with a multi-transistor NAND-string model. Key challenges in 3D NAND memory devices, such as (1) disturbance from pass voltages (V pass), (2) interference from neighboring wordlines, and (3) both the conventional and self-boost program inhibit operation of unselected bitlines, are addressed. For a target device structure, the operation voltages can be optimized to satisfy the requirement of (1)–(3). The stacking possibility of 3D NAND OS FeFETs is also predicted by conducting an extrapolation from the TCAD simulation results. We also studied the potential impact of in-plane polarization in the NAND FeFET string. A comparative study shows that in-plane polarization under the spacer may lead to unexpected characteristics of OS-channel FeFETs in 3D NAND memory operation. This paper will provide insights on the feasibility of 3D NAND FeFETs for high-capacity storage memory.