Mobility improvement in accumulation-mode GeOI pMOSFETs with back interface rearrangement by H2 annealing

Abstract

Abstract In this paper, we have demonstrated the high hole mobility in accumulation-mode Ge-on-insulator (AM-GeOI) pMOSFETs with back interface engineering by low-temperature H2 annealing. The hole mobility of 227 cm2 V−1 s−1 was obtained for the device annealed at 400 °C in H2 ambient, which is 32% higher than that of the control device. A significant improvement in carrier mobility was attributed to two main factors: (1) the atomic rearrangement of Si and Ge in the intermixing layer located at the back interface, and (2) partial relaxation of tensile strain by thermal treatment.