Filling of Very Fine Via Holes for Three-Dimensional Packaging by Using Ionized Metal Plasma Sputtering and Electroplating
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Reference4 articles.
1. Copper electroplating to fill blind vias for three-dimensional integration
2. Back side exposure of variable size through silicon vias
3. Current Status of Research and Development for Three-Dimensional Chip Stack Technology
4. Effects of Electroplating Parameters on the Defects of Copper via for 3D SiP
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1. Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer;Japanese Journal of Applied Physics;2019-05-23
2. Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer;Japanese Journal of Applied Physics;2017-06-27
3. Pretreatment to assure the copper filling in through-silicon vias;Journal of Materials Science: Materials in Electronics;2016-04-07
4. Copper seed layer repair using an electroplating process for through silicon via metallization;Microelectronic Engineering;2013-05
5. Analysis of a metal filling and liner formation mechanism of the blind via with nano-Ag particles for TSV (through silicon via) interconnection;Journal of Micromechanics and Microengineering;2012-06-20
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