Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature-Reference-Cited by-同舟云学术

Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature

Published:2007-12-14 Issue:No. 49 Volume:46 Page:L1228-L1230
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Cho Hyun-Jun,Hong Wan-Shick,Lee Sung-Hyun,Kim Tae-Hwan,Lee Kyung-Min,Park Kyung-Bae,Jung Ji-Sim,Kwon Jang-Yeon

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference12 articles.

1. Microcrystalline silicon films deposited by hot-wire CVD for solar cells on low-temperature substrate

2. Formation of low-resistivity poly-Si and SiNx films by Cat-CVD for ULSI application

3. Silicon for thin-film transistors

4. Low temperature polysilicon TFTs: a comparison of solid phase and laser crystallization

5. Amorphous Silicon Film Deposition by Low Temperature Catalytic Chemical Vapor Deposition (<150 °C) and Laser Crystallization for Polycrystalline Silicon Thin-Film Transistor Application

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characteristics of bottom-gate low temperature nanocrystalline silicon thin film transistor fabricated by hydrogen annealing of gate dielectric layer;Thin Solid Films;2010-09

2. Effect of In Situ Hydrogen Annealing on Dielectric Property of a Low Temperature Silicon Nitride Layer in a Bottom-Gate Nanocrystalline Silicon TFT by Catalytic CVD;ECS Transactions;2010-04-16

3. Nanocrystalline silicon films deposited with a modulated hydrogen dilution ratio by catalytic CVD at 200°C;Current Applied Physics;2009-03