Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source-Reference-Cited by-同舟云学术

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Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

Published:2008-04-25 Issue:4 Volume:47 Page:2593-2597
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Toh Eng-Huat,Wang Grace Huiqi,Chan Lap,Sylvester Dennis,Heng Chun-Huat,Samudra Ganesh S.,Yeo Yee-Chia

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference7 articles.

1. Device scaling limits of Si MOSFETs and their application dependencies

2. Experimental Study of Two-Dimensional Confinement Effects on Reverse-Biased Current Characteristics of Ultrathin Silicon-on-Insulator Lateral, Unidirectional, Bipolar-Type Insulated-Gate Transistors

3. Revised Shockley–Read–Hall lifetimes for quantum transport modeling

4. Complementary tunneling transistor for low power application

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1. Ultra Low Power and High Speed Electronic Circuits Using Double Gate Tunnel Field Effect Transistor;Journal of The Institution of Engineers (India): Series B;2024-08-01

2. Analog performance and linearity analysis of a p-type group IV-IV SiGe TFET;Journal of Computational Electronics;2024-03-19

3. Investigation of hetero gate oxide hetero stacked triple metal vertical tunnel FET with variable interface trap charges and temperature;Microelectronics Journal;2024-01

4. Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET;IEEE Access;2022

5. Analysis of Temperature Dependent Effects on DC, Analog/RF and Linearity Parameters for a Delta Doped Heterojunction Vertical tunnel FET;Silicon;2021-11-03

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