In-Situ Deposition of High-k Gate Stack on InGaAs and GaAs for Metal-Oxide-Semiconductor Devices with Low Equivalent Oxide Thickness

Abstract

We have demonstrated that Fermi level pinning at the interface between InGaAs or GaAs and HfO2 gate dielectric can be prevented by an in-situ deposited amorphous silicon interface passivation layer. A fully in-situ process of III-V surface passivation and high-k gate stack deposition allows scaling of the Si passivation layer thickness thus resulting in significant reduction of equivalent oxide thickness (EOT) for InGaAs and GaAs Metal Oxide Semiconductor (MOS) devices. A low EOT of 1.6 nm was obtained for 10 nm HfO2 for both n-type and p-type GaAs and InGaAs MOS Capacitors. Good control of the drain current by gate voltage was observed on depletion mode a-Si passivated GaAs MOS transistors.