1. S. Casimirus , in
Proceedings of 3D Chip Stacking Symposium
, K. Kondo , Editor, The Electronics Division of Chemical Engineering, p. 106 (2009).
2. ASET, Annual Report of Electronics SI (1999, 2000).
3. K. Takahashi, Y. Taniguchi, M. Tomisaka, H. Yonemoto, M. Hoshino, M. Ueno, Y. Egawa, Y. Nemoto, T. Yonezawa, and K. Kondo , in
Electronic Components and Technology Conference
, ASET and Okayama University, p. 601 (2004).
4. High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
5. High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking