(Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies

Abstract

We report on gate-all-around (GAA) vertically stacked lateral nanowires (NW) and nanosheets (NS) FET devices as promising candidates to replace finFETs and help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes. In addition, GAA vertical NW/NS FETs appear particularly attractive for enabling highly dense memory cells such as ultra-scaled MRAMs with lower energy consumption and smaller access latency values. Key fabrication challenges and device features for both types of transistors will be discussed here, together with the possibility to manufacture them on the same wafer by a cost-effective, co-integration scheme to obtain simultaneously a high-performance logic platform and have increased on-chip memory content.