Device and Circuit Level Assessment of Negative Capacitance TFETs for Low-Power High-Performance Digital Circuits

Abstract

In this paper, we propose and analyse the performance of negative capacitance tunnel field-effect-transistors (NC-TFETs) at device and circuit level. We design and simulate four NC-TFETs, two are Silicon based “Si NC N-TFET,” “Si NC P-TFET” and two are Heterojunction Silicon-Germanium source based “SiGe NC N-TFET,” “SiGe NC P-TFET.” The effect of NC is incorporated with 5 nm thick layer of ferroelectric Hafnium Zirconium Oxide HfZrO2 (FE-HZO) in gate stack of TFETs by using of Landau-Khalatnikov (L-K) equations in MATLAB. The results show that at reduced NC gate voltage, the ON current (ION), On to OFF current (ION/IOFF) in NC devices is enhanced by ∼ 100 % , while ∼ 50 % reduction in the threshold voltage (VTH) and Average subthreshold slope (SSAV) is observed. The SiGe NC-TFETs showed the best response with maximum ION ∼ 10 − 5 A μ m range, ION/IOFF ratio of ∼ 10 11 , lowest SS ∼ 25 mv decade − 1 , as compare to Si NC-TFETs. The circuit transient analysis is done using the Verilog-A model based on look-up table (LUT) approach. The propagation delay of NC NAND circuits is reduced ∼ 90%, the SiGe NC-TFETs based circuits showing the smallest propagation delay and fast transient characteristics. This paper also demonstrates that the impact of FE-HZO thickness (TFE) on the device-circuit characteristics.