Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Abstract

The Nanosheet FET (NS FET) has proven to be a potential candidate for sub-5-nm nodes. For the first time, in this manuscript, the NS FET performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the analog/RF figures of merit (FOMs) are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. The crucial circuits for IC design such as inverter, ring oscillator, and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures.