Current Status of Slurries and Cleans for CMP of III-V Device Fabrications – A Critical Review

Abstract

With the growth of cloud computing market, the need for logic and memory chips for data centers have been steadily growing which require low power and high performance. Another area of growing semiconductor application is mobile products which require increasingly higher performance without sacrificing power. The above two requirements can only be achieved by scaling supply voltage (Vdd). III-V materials enable Vdd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si. For example, Vinj (InGaAs) > 2Vinj (Si) at less than half VDD. The development at Intel on InGaAs and at IMEC on Ge based FinFET structures have made it possible to conceive new integration schemes[1]. In order to enable such CMOS fabrication, development of CMP (Chemical Mechanical Planarization) slurry, post CMP clean and modification of the presently available process tools need to be done. While new slurries and cleans will be needed to planarize III-V film layer(s) without compromising the film composition (and functionality), modification of the process tool will be needed to address potential release of toxic waste water into the waste stream after planarization. In this paper, the status of development of CMP processes, slurries and post CMP cleans will be reviewed and the critical needs to enable for the future III-V device integration will be analyzed.