Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications

Abstract

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed when the substrate surface is passivated with a trap-rich layer of material, such as polysilicon. A technique to fabricate substrate-passivated HR SOI wafer is presented, where the wafers are obtained by bonding a polysilicon-passivated HR Si substrate with an oxidized donor substrate. Preliminary encouraging bonding test results are presented.