The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs

Abstract

Recently, best 65 nm Ge pMOSFET performance has been reported (13) with a standard Si CMOS HfO2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si-layer grown on the Ge surface. We investigated in more detail how device performance (hole mobility, Ion, Vt etc) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimized the process by switching to another Si precursor and lowering the deposition temperature. This resulted in a 4 times lower Dit and in improved device performance.