Advanced HDP STI Gap-Fill Development in 65nm Logic Device

Abstract

High density plasma chemical vapor deposition (HDP-CVD) has been proven to be a sucessful process for shallow trench isolation (STI) gap fill in advanced CMOS device fabrication. As CMOS technology nodes continue to shrink, STI gap-fill requirement become more and more challenging. To keep pace with the stringent requirements, a novel HDP gap-fill process - Integrated Proess Modulation (IPM) has been developed to fill these aggressive structures. IPM process, which is extending from Deposition - Etch - Deposition (DED) process, is made of a serial of deposition/etch cycles, which is one of techniques to keep trench open by using NF3-based plasma dry etch before the trench nearly closed by film deposition. Based on this process model, HDP gap-fill capability has been greatly extended to 65nm and beyond. This paper summarizes the STI gap-fill development and optimization work of IPM processes