Effect of Bias Frequency on Bottom-Up SiO2 Gap-Filling Using Plasma-Enhanced Atomic Layer Deposition

Author:

Shin Ye Ji1ORCID,Kim Ho Gon1,Choi Seung Yup1,Kim Seo Min2,Kang Ji Eun1,Han Hye Won3,Kim Ji Min3,Kim Geun Hwi1,Yeom Geun Young14ORCID

Affiliation:

1. Department of Advanced Materials and Science Engineering, Sungkyunkwan University (SKKU), Suwon-si, Gyeonggi-do 16419, Republic of Korea

2. School of Chemical Engineering, Sungkyunkwan University (SKKU), Suwon-si, Gyeonggi-do 16419, Republic of Korea

3. Department of Semiconductor Convergence Engineering, Sungkyunkwan University (SKKU), Suwon-si, Gyeonggi-do 16419, Republic of Korea

4. SKKU Advanced Institute of Nano Technology (SAINT), Sungkyunkwan University, Suwon-si, Gyeonggi-do 16419, Republic of Korea

Funder

Ministry of Trade, Industry and Energy

Korea Evaluation Institute of Industrial Technology

Publisher

American Chemical Society (ACS)

Reference22 articles.

1. Perspective: New process technologies required for future devices and scaling

2. Innovative Gap-Fill Strategy for 28 nm Shallow Trench Isolation

3. (Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

4. Review of Semiconductor Flash Memory Devices for Material and Process Issues

5. Tilke, A.; Culmsee, M.; Jaiswal, R.; Hampp, R.; Conti, R.; Galiano, M.; Stapelmann, C.; Wille, W.; Jain, A. STI Gap-fill technology with High Aspect ratio process for 45nm CMOS and beyond. In The 17th Annual SEMI/IEEE ASMC 2006 Conference, 2006; IEEE: pp 71–76.

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