Integration Challenges for Advanced Process-Strained CMOS on Biaxial-Strained-SOI (SSOI) Substrates

Abstract

This work reviews the integration of process-induced stressors into transistors fabricated on biaxially-strained-SOI substrates. Tensile and compressive overlayers, embedded-SiGe, and multiple stress memorization techniques have been evaluated on strained-SOI substrates. All process-induced strain techniques are compatible with strained-SOI, except for a stress memorization technique which requires amorphization of the source/drain regions. The compatible techniques increase NMOS drive current and PMOS drive current comparably on strained-SOI and standard unstrained-SOI. This results in no loss of short channel PMOS performance but only a moderate gain in short channel NMOS performance, when SSOI is compared to standard unstrained-SOI.