Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop-Reference-Cited by-同舟云学术

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Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

Published:1999-09-01 Issue:3 Volume:21 Page:1-5
ISSN:1225-6463
Container-title:ETRI Journal
language:en
Short-container-title:ETRI J

Author:

Song Jae Ho Song,Yoo Tae Whan Yoo,Ko Jeong Hoon Ko,Park Chang Soo Park,Kim Jae Keun Kim

Publisher

Wiley

Subject

Electrical and Electronic Engineering,General Computer Science,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Clock recovery circuits up to 20 Gbit/s for optical transmission systems

2. 20 Gbit/s DR based timing recovery circuit

3. A novel clock extraction circuit using a new NRZ-to-PRZ converter and a dielectric resonator filter for 10 Gbit/s optical receiver

4. A 50 MHz phase- and frequency-locked loop

5. A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits;ETRI Journal;2008-04-08

2. Mesoporous silicon: a platform for the delivery of therapeutics;Expert Opinion on Drug Delivery;2007-03

3. Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits;2006 IEEE MTT-S International Microwave Symposium Digest;2006

4. Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers;Microwave and Optical Technology Letters;2005

5. STM Study of DNA Films Synthesized on Si(111) Surfaces;Langmuir;2003-05-28

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