A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/2985/00090084.pdf?arnumber=90084
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance;IEEE Journal of Solid-State Circuits;2011-12
2. Design of high-speed clock and data recovery circuits;Analog Integrated Circuits and Signal Processing;2007-08-29
3. A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer;IEEE Journal of Solid-State Circuits;2005-02
4. Novel surface-mount-type fiber optic transmitter and receiver;Optoelectronic Interconnects VII; Photonics Packaging and Integration II;2000-04-27
5. Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop;ETRI Journal;1999-09-01
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