20 Gbit/s DR based timing recovery circuit
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19940518?crawler=true&mimetype=application/pdf
Reference4 articles.
1. 10 Gbit/s timing recovery circuit using dielectric resonator and active bandpass filters
2. Design and performance of clock recovery GaAs ICs for high-speed optical communication systems
3. Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme
4. Bit synchronization in multigigabit receivers
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1. Design and Implementation of Open-Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual-Mode Operation;ETRI Journal;2008-04-08
2. A Compact 43Gb/s Clock Recovery Module Using a Dielectric Resonator Filter;2006 IEEE LEOS Annual Meeting Conference Proceedings;2006-10
3. 100 Gbit/s optical clock recovery using electrical phaselocked loop consisting of commercially available components;Electronics Letters;2000
4. Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop;ETRI Journal;1999-09-01
5. All-optical fiber signal processing and regeneration for soliton communications;IEEE Journal of Selected Topics in Quantum Electronics;1997
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