Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications
Author:
Publisher
Wiley
Subject
Electrical and Electronic Engineering,General Computer Science,Electronic, Optical and Magnetic Materials
Reference7 articles.
1. Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
2. A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes
3. A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS
4. A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS
5. A 151-mm$^{2}$ 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology
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