1. Roughness characterization of gate all around Silicon NanoWire fabrication;Levi,2012
2. 22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP);Bencher,2008
3. Innovative self-aligned triple patterning for 1x half pitch using single “spacer deposition-spacer etch” step;Mebarki,2011