Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography-Reference-Cited by-同舟云学术

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography

Published:2016-02-03 Issue:2 Volume:15 Page:021202
ISSN:1932-5150
Container-title:Journal of Micro/Nanolithography, MEMS, and MOEMS
language:en
Short-container-title:J. Micro/Nanolith. MEMS MOEMS

Author:

Xu Xiaoqing¹,Cline Brian²,Yeric Greg²,Yu Bei³,Pan David Z.¹

Affiliation:

1. The University of Texas at Austin, ECE Department, 201 East 24th Street, Stop C8800, Austin, Texas 78712, United States

2. ARM Inc., 5707 Southwest Parkway #100, Austin, Texas 78735, United States

3. Chinese University of Hong Kong, CSE Department, Shatin, NT, Hong Kong

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference31 articles.

1. Decomposition-aware standard cell design flows to enable double-patterning technology

2. Design for Manufacturing With Emerging Nanolithography

3. Implications of triple patterning for 14nm node design and patterning

4. Intel sees quad-patterned path to 10-nm chips;Merritt,2012

5. Self-aligned double patterning aware pin access and standard cell layout co-optimization;Xu,2014

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