1. [1] Ahrens, M., Gester, M., Klewinghaus, N., Muller, D., Peyer, S., Schulte, C. and Tellez, G.: Detailed routing algorithms for advanced technology nodes, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.34, No.4, pp.563-576 (2015).
2. [2] Anderson, B.A., Bickford, J.P., Buehler, M., Hibbeler, J.D., Koehl, J. and Nowak, E.J.: Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same (2012). US Patent 8,234,594.
3. [3] Arnold, J.C., Burns, S.D., Kanakasabapathy, S.K. and Yin, Y.: Self aligning via patterning (2012). US Patent 8,298,943.
4. [4] Bickford, J., Bühler, M., Hibbeler, J., Koehl, J., Müller, D., Peyer, S. and Schulte, C.: Yield improvement by local wiring redundancy, IEEE Proc. International Symposium on Quality Electronic Design (ISQED), pp.6 pp.-478 (2006).
5. [5] Chang, F.-Y., Tsay, R.-S. and Mak, W.-K.: How to consider shorts and guarantee yield rate improvement for redundant wire insertion, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.33-38 (2009).