Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow-Reference-Cited by-同舟云学术

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Published:2014-01-21 Issue:1 Volume:13 Page:011203
ISSN:1932-5150
Container-title:Journal of Micro/Nanolithography, MEMS, and MOEMS
language:en
Short-container-title:J. Micro/Nanolith. MEMS MOEMS

Author:

Kteyan Armen¹,Gevorgyan Gevorg¹,Hovsepyan Henrik¹,Choy Jun-Ho²,Sukharev Valeriy²

Affiliation:

1. Mentor Graphics Corporation, Yerevan 0012, Armenia

2. Mentor Graphics Corporation, Fremont, California 94538

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. TechTuning: stress management for 3D through-Si-Via stacking technologies;Radojcic,2011

2. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

3. 3D Integration for energy efficient system design;Borkar,2009

4. Reliability challenges in 3D IC packaging technology

5. Impact of flip-chip packaging on copper/low-k structures

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3. IC package related stress effects on the characteristics of ring oscillator circuits;2021 22nd International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE);2021-04-19

4. Analysis of the Effect of TSV-Induced Stress on Devices Performance by Direct Strain and Electrical Measurements and FEA Simulations;IEEE Transactions on Device and Materials Reliability;2017-12

5. Effects of Stress and Electromigration on Microstructural Evolution in Microbumps of Three-Dimensional Integrated Circuits;IEEE Transactions on Device and Materials Reliability;2014-12