Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance-Reference-Cited by-同舟云学术

Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance

Published:2022-04-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2022 International Symposium on Physical Design
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Author:

Kteyan Armen¹,Choy Jun-Ho²,Sukharev Valeriy²,Bertoletti Massimo³,Maiorca Carmelo³,Zadra Rossana³,Inzaghi Massimo³,Gattere Gabriele⁴,Zinco Giancarlo⁴,Valente Paolo⁴,Bardelli Roberto⁴,Valerio Alessandro⁴,Rolandi Pierluigi⁴,Monetti Mattia⁴,Cuomo Valentina⁴,Santapà Salvatore⁴

Affiliation:

1. Siemens EDA, Yerevan, Armenia

2. Siemens EDA, Fremont, CA, USA

3. Siemens EDA, Milano, Italy

4. STMicroelectronics, Milano, Italy

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3505170.3511798

Reference8 articles.

1. R. Radojcic More-than-Moore 2.5D and 3D SiP Integration Springer 2017. R. Radojcic More-than-Moore 2.5D and 3D SiP Integration Springer 2017.

2. Radojcic, R., Nowak, M., and Nakamoto, M ., 2011, "TechTuning: Stress management for 3D Through-Si-Via stacking technologies ", International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, AIP Conf. Proc. 1378 , pp. 5 -- 20 . Radojcic, R., Nowak, M., and Nakamoto, M., 2011, "TechTuning: Stress management for 3D Through-Si-Via stacking technologies", International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, AIP Conf. Proc. 1378, pp. 5--20.

3. Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction

4. Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

5. V. Sukharev , A. Kteyan , J. Choy , "An accurate assessment of Chip-Package Interaction is a key factor for designing resilient 3D IC systems", 2019 International 3D Systems Integration Conference (3DIC) , Sedai , Japan , 2019 . V. Sukharev, A. Kteyan, J. Choy, "An accurate assessment of Chip-Package Interaction is a key factor for designing resilient 3D IC systems", 2019 International 3D Systems Integration Conference (3DIC), Sedai, Japan, 2019.