Author:
Rovner Vyacheslav V.,Jhaveri Tejas,Morris Daniel,Strojwas Andrzej,Pileggi Larry
Cited by
5 articles.
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1. Logic IP for Low-Cost IC Design in Advanced CMOS Nodes;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-02
2. Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip;Journal of Micro/Nanolithography, MEMS, and MOEMS;2014-12-30
3. Design implications of extremely restricted patterning;Journal of Micro/Nanolithography, MEMS, and MOEMS;2014-10-03
4. Talbot effect immersion lithography by self-imaging of very fine grating patterns;Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena;2012-11
5. Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node;Design for Manufacturability through Design-Process Integration VI;2012-03-29