1. Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress
2. Lithography overlay control improvement using patterned wafer geometry for sub 22 nm technology nodes;Peterson,2015
3. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices;Lee,2015
4. A study of feed-forward strategies for overlay control in lithography processes using CGS technology;Anberg,2015
5. Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems;Brunner,2016