Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design
Author:
Affiliation:
1. System IC R&D Lab., LG Electronics, Seoul 137-893, Republic of Korea
2. University of Texas, Department of Electrical and Computer Engineering, Austin, Texas 78712, United States
Publisher
SPIE-Intl Soc Optical Eng
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference26 articles.
1. A new graph theoretic, multi objective layout decomposition framework for double patterning lithography;Yang,2010
2. Electrical impact of line-edge roughness on sub-45-nm node standard cells
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4. Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography
5. Double patterning lithography for 32nm: critical dimensions uniformity and overlay control considerations
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4. Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices;ECS Journal of Solid State Science and Technology;2019
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