Implementation of high speed 64-bit MAC unit using FPGA-Reference-Cited by-同舟云学术

Implementation of high speed 64-bit MAC unit using FPGA

Published:2022 Issue: Volume: Page:
ISSN:0094-243X
Container-title:INTERNATIONAL CONFERENCE ON RESEARCH IN SCIENCES, ENGINEERING & TECHNOLOGY
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Author:

Anuradha P.,Rajkumar K.,Arabelli Rajeshwarrao,Shareena R.

Publisher

AIP Publishing

Link

http://aip.scitation.org/doi/pdf/10.1063/5.0081885

Reference15 articles.

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4. Poornima M, Patil SK, Shivukumar SK, Sanjay H. Implementation of multiplier using Vedic algorithm. International Journal of Innovative Technology and Exploring Engineering (IJITEE). 2013 May;2(6):219–23.

5. Akhter S, Saini V, Saini J. Analysis of Vedic multiplier using various adder topologies. In 4th International Conference on Signal Processing and Integrated Networks (SPIN) 2017 Feb 2 (pp. 173–176). IEEE.

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