Vedic Mathematics Based Multiply Accumulate Unit

Author:

Jaina Devika,Sethi Kabiraj,Panda Rutuparna

Publisher

IEEE

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Vedic mathematics for sustainable knowledge: a systematic literature review;International Journal of Comparative Education and Development;2024-07-11

2. Design of a Vedic Multiplier based 64-bit Multiplier Accumulator Unit;2024 5th International Conference on Innovative Trends in Information Technology (ICITIIT);2024-03-15

3. A 64 BIT MAC Unit Design based on FPGA Using Vedic Multiplier;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

4. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders;Engineering, Technology & Applied Science Research;2023-06-02

5. Design and Analysis of Low Power MAC for DSP Processor;2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1);2023-04-21

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