Design of a Vedic Multiplier based 64-bit Multiplier Accumulator Unit
Author:
Affiliation:
1. Amrita Vishwa Vidyapeetham,Amrita School of Engineering,Department of Electronics and Communication Engineering,Coimbatore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10579969/10579987/10580179.pdf?arnumber=10580179
Reference17 articles.
1. Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters
2. Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit
3. Design of High-Speed and Energy-Efficient Parallel Prefix Kogge Stone Adder
4. Power and delay analysis of CMOS multipliers using Vedic algorithm
5. Design of a High-Speed Binary Counter Using a Stacking Circuit
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