Suppression of positive bias instability by inserting polarized AlN interlayer at AlSiO/p-type GaN interface in metal–oxide–semiconductor field-effect transistor

Abstract

Bias instability is a critical issue for metal–oxide–semiconductor field-effect transistors (MOSFETs). This study demonstrates suppression of the positive bias instability of the threshold voltage (Vth) in a GaN MOSFET by insertion of a thin crystalline AlN interlayer (AlN-IL) formed by plasma-enhanced atomic layer deposition. The gate stacks were composed of an AlSiO/AlN/p-type GaN structure having a high channel mobility of greater than 170 cm2 V−1 s−1. When the AlN-IL was inserted, the Vth shift under an oxide electric field of 3.9 MV cm−1 was strongly suppressed from 0.72 V to less than 0.12 V. This suppression was attributed to an increase in the effective barrier height associated with oxide traps in the AlSiO for inversion channel electrons as a result of the insertion of the polarized AlN-IL. The key to this approach is adequate control of the AlN-IL thickness. The insertion of a 0.8-nm-thick AlN-IL led to a low interface state density (Dit) and a minimized positive bias instability, whereas an AlN-IL thicker than 2.3 nm led to an increase in both Dit and a Vth shift. The effective barrier height should increase with increasing AlN thickness; however, an increase in a Vth shift instead occurred. This indicates that defects that capture electrons are additionally introduced when the thickness of the AlN-IL on GaN layers exceeds the critical thickness. The results clearly suggest that Vth instability can be minimized by controlling the thickness of a thin AlN-IL deposited at an AlSiO/p-type GaN interface and simultaneously providing high channel mobility.