Strain mapping of Si devices with stress memorization processing
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4816743
Reference19 articles.
1. Fabrication and analysis of deep submicron strained-Si n-MOSFET's
2. Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
3. Nanoscale holographic interferometry for strain measurements in electronic devices
4. Off-axis electron holography with a dual-lens imaging system and its usefulness in 2-D potential mapping of semiconductor devices
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1. A finite element method to simulate dislocation stress: A general numerical solution for inclusion problems;AIP Advances;2020-01-01
2. Strain mapping at the interface of InP/In x Ga1-x As/InP as measured by the scanning transmission electron microscope-moiré fringe method;Applied Physics Express;2019-10-01
3. Stress mapping of a strain superlattice using scanning moiré fringe imaging;Applied Physics Letters;2018-07-16
4. Strain mapping of semiconductor specimens with nm-scale resolution in a transmission electron microscope;Micron;2016-01
5. Formation of multiple dislocations in Si solid-phase epitaxy regrowth process using stress memorization technique;Computational Materials Science;2015-06
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