Threshold voltage instability in III-nitride heterostructure metal–insulator–semiconductor high-electron-mobility transistors: Characterization and interface engineering

Author:

Huang Sen12ORCID,Wang Xinhua12ORCID,Yao Yixu12ORCID,Deng Kexin12ORCID,Yang Yang12ORCID,Jiang Qimeng12ORCID,Liu Xinyu12ORCID,Guo Fuqiang3ORCID,Shen Bo3,Chen Kevin J.4ORCID,Hao Yue5ORCID

Affiliation:

1. High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics of Chinese Academy of Sciences 1 , Beijing 100029, China

2. University of Chinese Academy of Sciences 2 , Beijing 100049, China

3. School of Physics, Peking University 3 , Beijing 100871, China

4. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology 4 , Clear Water Bay, Kowloon, Hong Kong

5. School of Microelectronics and the State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, Xidian University 5 , Xi'an 710071, China

Abstract

III-nitride heterostructure-based metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), compared with Schottky and p-GaN gate HEMTs, have demonstrated significant potential in the next-generation high-power electronic devices due to their exceptional gate reliability. This study presents a comprehensive investigation of threshold voltage (VTH) instability in III-nitride heterostructure-based MIS-HEMTs, with a specific emphasis on the interfaces of the multi-heterostructures. Two widely studied amorphous materials, namely, Al2O3 and SiNx, have been extensively examined as primary gate insulators in GaN-based MIS-HEMTs. To efficiently remove native oxides from the (Al)GaN surface, a novel in situ high-temperature remote plasma pretreatment (RPP) technique has been developed. This technique involves sequential application of NH3/N2 plasmas on the (Al)GaN surface before depositing the gate insulators using plasma-enhanced atomic layer deposition. The remarkable RPP process has proven to be a highly effective method for revealing atomic steps on the GaN surface, irrespective of whether the surface has undergone oxidation or etching processes. To further enhance the interface quality and potentially reduce bulk traps in the gate insulator, optimization of deposition temperature and post-deposition annealing conditions have been explored. Additionally, an electron-blocking layer, such as SiON, is incorporated into the MIS-HEMTs to prevent electron injection into bulk traps within the insulator. Novel characterization techniques including constant-capacitance and isothermal-mode deep-level transient spectroscopy have also been developed to explore the failure mechanisms in MIS-HEMTs. These techniques allow for the differentiation between bulk traps in the GaN epitaxy and those present within the gate insulators. This in-depth physical understanding provides valuable insights into the sources of failure in GaN-based MIS-HEMTs.

Funder

National Key Research and Development Program of China

Youth Innovation Promotion Association of the Chinese Academy of Sciences

CAS-Croucher Funding Scheme for Joint Laboratories

National Natural Science Foundation of China

Beijing Municipal Science and Technology Commission, Adminitrative Commission of Zhongguancun Science Park

Publisher

AIP Publishing

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