Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

Abstract

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.