A model of electrical conduction across the grain boundaries in polycrystalline-silicon thin film transistors and metal oxide semiconductor field effect transistors
Author:
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.3173179
Reference37 articles.
1. On-current modeling of large-grain polycrystalline silicon thin-film transistors
2. An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor
3. Modeling of laser-annealed polysilicon TFT characteristics
4. The dc voltage dependence of semiconductor grain‐boundary resistance
5. Field-effect analysis for the determination of gap-state density and Fermi-level temperature dependence in polycrystalline silicon
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1. High Hole Mobility Inorganic Halide Perovskite Field‐Effect Transistors with Enhanced Phase Stability and Interfacial Defect Tolerance;Advanced Electronic Materials;2021-10-15
2. Effect of Grain Boundaries on the Performance of Thin-Film-Based Polycrystalline Silicon Solar Cells: A Numerical Modeling;Journal of Materials Engineering and Performance;2018-01-29
3. Explicit calculation for grain boundary barrier height in polysilicon TFTs based on quasi-two-dimensional approach;Solid-State Electronics;2013-09
4. High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization;Japanese Journal of Applied Physics;2012-09-20
5. High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization;Japanese Journal of Applied Physics;2012-09-01
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